DRDIC'26

Abstract

Edge intelligence holds immense importance in enabling real-time decision-making and reducing latency by processing data closer to sensing. This approach enhances efficiency, privacy, and security by minimizing the need for constant data transmission to centralized servers. However, the tradeoffs lie in the limited computational power and memory at the edge, potentially restricting the complexity of algorithms and the scale of data processed compared to the vast resources available in the cloud.

This talk presents the fusion of AI with sensors, showcasing the integration of AI at an embryonic stage with sensors, leading to a profound impact on sensor functionality and application. The talk will illustrate this transformative integration of AI at the sensor level using three compelling case studies.

Olfaction. The convergence of bio-inspired classification algorithms with gas and smell sensors presents a breakthrough in realizing an electronic nose. The seamless embedding of AI augments sensor capabilities, enabling training, recognition and classification of diverse odors, mirroring the sophistication of the human olfactory system.

Vision. Minor modifications of the pixel structure can accommodate convolutional layers for deep learning. This adaptation amplifies the capacity of vision sensors, empowering them to interpret and process visual data with the sophistication characteristic of deep learning models, enabling efficient integration of deep learning at the sensor level.

Wearables. The integration of AI with wearable sensors allows the classification of signals derived from wearable devices, enabling the discrimination of various gestures, biomechanics, and vital signs. By embedding AI within these sensors, a new paradigm in healthcare monitoring and patient care unfolds, revolutionizing the real-time analysis and interpretation of physiological data.

In a nutshell, this talk unravels the paradigm shift where AI converges with sensors at the edge, augmenting their capabilities and reshaping possibilities across olfaction, vision, and wearable sensor domains. It not only unveils technical advancements in the area but also underscores the transformative potential of extreme edge intelligence in diverse fields.

Abstract

Custom integrated circuits are central to modern scientific instrumentation, enabling the precise measurement of extremely small and fast signals in fields such as particle physics, medical imaging, environmental monitoring, and advanced sensing.

This talk introduces analog and mixed-signal IC design through practical examples of scientific readout ASICs developed for diamond detectors, graphene sensors, LGAD timing detectors, and CERN experiments. It provides a concise overview of the complete ASIC development process, from system specifications and circuit architecture to physical design, fabrication, and experimental testing.

The talk will also explore opportunities for Algeria to build a fabless microelectronics ecosystem through specialized education, shared design infrastructure, international partnerships, and engagement with the Algerian scientific diaspora. The objective is to highlight a realistic path towards developing local expertise in ASIC design for scientific, medical, energy, agricultural, telecommunications, and space applications.

Abstract

The rapid development of electric and smart vehicles is driving a growing demand for advanced semiconductor technologies. Modern electric vehicles integrate thousands of semiconductor devices, making integrated circuit design a critical component of automotive innovation. This talk provides an overview of the automotive semiconductor ecosystem, highlighting key market trends, the major automotive semiconductor companies, and the growing role of ICs in electric and intelligent vehicles.

It then introduces the smart power path and discusses the main principles involved in automotive IC design. Particular attention is given to the V-Model design flow, covering the stages from specification and design through to verification and validation. The talk also surveys the landscape of mixed-signal simulation tools and presents a typical pre-silicon verification flow, showing why simulation and verification matter so much before fabrication.

The aim is a practical overview of the automotive IC design ecosystem — from market needs and system architecture to design methodologies, simulation tools and pre-silicon verification — while emphasising the challenges of developing reliable, high-performance automotive semiconductor solutions.

Abstract

This talk introduces open-source integrated-circuit design using the IHP open Process Design Kits (PDKs) and a modern open-source EDA toolchain. IHP is a European research institute with long-standing expertise in semiconductor technologies, device modeling, and silicon fabrication. Its open PDKs provide access to technologies such as SG13G2 and SG13CMOS5L, enabling researchers, students, and engineers to develop designs for mature silicon processes.

The presentation first provides an overview of these technologies, their main features, and their potential applications in analog, mixed-signal, and digital circuit design. It then introduces the principal components of an open PDK: device models, parameterized cells, design rules, design libraries for digital design, and documentation.

The complete design flow is subsequently outlined using open-source tools such as Xschem, Qucs-S, ngspice, Gnucap, KLayout, openEMS, AWS Palace and LibreLane. The discussion covers schematic entry, circuit simulation, layout creation, design-rule checking, layout-versus-schematic verification, parasitic extraction, post-layout simulation, and electromagnetic simulation.

The talk concludes with an introduction to multi-project wafer (MPW) fabrication opportunities, including the submission process, design requirements, and the review performed before manufacturing. This overview demonstrates how open PDKs and open-source tools can lower barriers to IC design, support education and research, and enable the development of real, manufacturable silicon.

Abstract

This talk introduces an integrated lab-on-a-chip platform that unites digital microfluidics (DMF) with a CMOS-based electrochemical sensing interface for multi-sensor Salmonella detection. The system combines programmable, droplet-level fluid manipulation with real-time electrochemical quantification in a single compact, modular design.

Through an upgraded controller board, the sensor array was scaled from 2–3 to 5 fully functional electrodes, enabling parallel electrochemical sensing. Cyclic voltammetry measurements across scan rates of 10–100 mV/s demonstrated excellent linearity (R² > 0.96), near-ideal reversibility (I_PA/I_PC ratio between 0.98 and 1.02), and enhanced sensor-to-sensor reproducibility, with the coefficient of variation improving from roughly 8–10 % down to 4–6 %.

Alongside this, a fully integrated on-chip potentiostat and analog-to-digital converter were designed and fabricated in 65 nm CMOS technology to support differential pulse voltammetry. The design incorporates a three-electrode configuration and a split-reference low-voltage scheme, along with dedicated analog blocks for signal buffering, control amplification, and differential output generation.

Post-layout simulations across process corners confirmed strong, stable performance — gain exceeding 82 dB, a unity-gain bandwidth of 2.1 MHz, a 63° phase margin, input-referred noise of 28 nV/√Hz, and quiescent power of only 28 µW — all within a compact 2 mm × 1 mm die.

Collectively, these results highlight a scalable, low-power and highly reproducible biosensing platform, marking a meaningful step toward miniaturized, point-of-care diagnostic solutions.

Abstract

AI computation, whether for inference or training, is driving one of the most fundamental revolutions in the area of computer architecture. It is important to examine a survey of the technologies currently used to achieve the continuously expanding demand for AI computation power in the datacenter.

Building blocks like matrix processing accelerators, massively distributed caches and customized CPUs are used to handle LLMs whose size can reach a few terabytes.